makefile - Using GNU Make with subdirectories -

i wondering different approaches of using make in project subdirectories exist, , advantages/drawbacks, never see summary or cookbook.

i have seen in researches "recursive" , "single makefile" approaches, there others ?

i assume there not 1 "recursive" or "single makefile" approaches several, sum ?

for particular case, directory architecture looking this:

. ├── build │   ├── *.d │   ├── *.o |   ├── subdir1 |   │   ├── *.d |   │   └── *.o |   └── subdir2 |       ├── *.d |       ├── *.o |       └── subdir3 |           ├── *.d |           └── *.o ├── include │   ├── *.h │   └── *.h ├── makefile └── src     ├── *.c     ├── *.h     ├── subdir1     │   ├── *.c     │   └── *.h     └── subdir2         ├── *.c         ├── *.h         └── subdir3             ├── *.c             └── *.h 

which solution should choose ? possibly 1 allow source files same name ?

your project setup basic, should makefile:

src_dir := src bld_dir := build  src := $(shell find $(src_dir) -name "*.c") obj := $(src:$(src_dir)/%.c=$(bld_dir)/%.o) dep := $(obj:.o=.d)  cppflags := -mmd -mp # enable auto-dependency generation cflags   := -wall -w -pedantic  .phony: clean  all: $(obj)  clean:     $(rm) -r $(bld_dir)  .secondexpansion: $(bld_dir)/%.o: $(src_dir)/%.c | $$(@d)/ # first check destination directory exists     $(cc) $(cppflags) $(cflags) -o $@ -c $<  %/:     mkdir -p $* # -p flag necessary recursive directory creation  ifeq "$(makecmdgoals)" "" -include $(dep) endif 

the idea here list source files recursively using find command, supply make appropriate pattern rule compile in right place , pass right preprocessor file compiler enable auto-dependency generation.

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tested gnu make 4.1 under windows 8.1 git bash shell , following directory structure:

. ├── makefile └── src     ├── test.c     ├── test1.c     └── subdir1         └── test.c