fpga - Where's the latch in my VHDL program? -

i have latch involving signal d_reg in code. i'm new vhdl , can't seem find reason latch. i've assigned d_reg value every case of in_data. explain why have latch, , how prevent in future?

the warning receive is:

warning:xst:1710 - ff/latch <d_reg_0> (without init value) has constant value of 0 in block <delay_incrementor>. ff/latch trimmed during optimization process.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity delay_incrementor     port ( clk,reset: in std_logic;            in_data : in  std_logic_vector (7 downto 0);            out_data : out  std_logic_vector (7 downto 0);            d : out  std_logic_vector (25 downto 0)); end delay_incrementor;  architecture behavioral of delay_incrementor   signal d_reg,d_next: std_logic_vector (25 downto 0); begin   --register   process(clk,reset)   begin     if reset='1'       d_reg <= (others => '0');     elsif (clk='1' , clk'event)       d_reg <= d_next;     end if;   end process;    --next-state logic   d_next <= std_logic_vector(unsigned(d_reg) + "1001100010010110100000000") when in_data = "01010101" else              std_logic_vector(unsigned(d_reg) + "1001100010010110100000000") when in_data = "01000100" else              d_reg;   out_data <= "00010111" when in_data /= "00000000" else                 (others=>'0');    --output logic   d <= d_reg; end behavioral; 

xst warning 1710 common warning memory elements (latches, flip flops, ...).

the warning notes ff has constant value, possible d input or ce clock enable not used or change or trimmed :).

a latch found warning xst warning 737:

warning:xst:737 - found n-bit latch signal .