Verilog : Can't understand the resulting simulation (delay, blocking/non blocking) -

i'm studying verilog language (i have worked vhdl) , don't understand simulation of following code :

module exam2011; integer a,b,c,d; begin c = #1 a;  #2 b=a; d = a; end  initial begin       = 0; b = 0; c = 0; d = 0;      #1 a=1;      #2 a=2;      #2 a=3;      #2 a=4;      #2 a=5; end initial $monitor($time, “a=%d, b=%d, c=%d, d=%d”,a,b,c,d); endmodule 

the result :

#                    0a=          0, b=          0, c=          0, d=          0 #                    1a=          1, b=          0, c=          x, d=          0 #                    3a=          2, b=          1, c=          x, d=          1 #                    4a=          2, b=          1, c=          1, d=          1 #                    5a=          3, b=          1, c=          1, d=          1 #                    6a=          3, b=          3, c=          1, d=          3 #                    7a=          4, b=          3, c=          3, d=          3 #                    9a=          5, b=          5, c=          3, d=          5 #                   10a=          5, b=          5, c=          5, d=          5 

first, don't know if think in way : when change value of "a" , value of "b" , "d" (which "a") @ same time, how theses changes performed ? also, don't understand how interpret delay command # after assignment "=".

thanks help.

output depends upon simulator. 'always' , 'initial' statements executed in parallel. though looks parallel us, executed in sequence simulator in same time stamp.

after events in current time stamp done, simulator increment time stamp. in code, looks 'always' statement executed before 'initial' statement. let me try explain bit clearly.

c = #1 a; 

this statement equivalent to

temp = a; //sample value of 'a' #1;       // wait 1 unit of time c = temp; //assign sampled value 'c' 

since 'always' statement enters 1st simulator queue, samples value of 'a' 'x' , stores in temporary variable @ 0th time. enters 'initial' statement , assigns 0 'a','b','c' , 'd'. after #1 time unit, sampled value of 'a' 'x' assigned 'c' in 'always' statement.

#2 b = a; 

this statement equivalent to

#2 //wait 2 time unit  b = //sample value of 'a' , assign b 

after 3 time unit, since 'always' block in top of simulator queue, value of 'a' still '1' , gets assigned 'c'. after 'initial' statement executed , value of '2' assigned 'a'. rest of output, behaves in same fashion. hope helps.